This disclosure is related to controlling an output signal with frequency and phase precisely related to the frequency and phase of an input “reference” signal, more particularly to phase locked loop (PLL) control.
PLL control circuits are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Traditionally, the PLL circuit has been an analog block, including the basic components of a voltage control oscillator (VCO), phase and frequency detector (PFD), charge pump, low pass filter (LPF) and a feedback path. However, such analog PLL circuits comprise a plurality of capacitors which require a significantly large chip area. Additionally these circuits are very sensitive to power noise.
More recently, PLL circuit design has evolved to a greater use of digital control. The first generation digital PLL uses one external high frequency clock to sample the reference clock, then generate the output clock by dividing or multiplying a certain number according to requirement. The frequency of an external clock having accuracy required by such PLL circuit is limited with respect to its capability for applying a sampling rate that can accommodate high frequency reference clock signals. As this design can only be used in low frequency applications, a hybridization of analog and digital elements has been pursued. With such approach, chip area has not been significantly reduced, while performance is markedly decreased.
A need thus exists for a digital PLL circuit that is not limited to the existing PLL structures. Performance capabilities, such as high DCO frequency range, long term jitter control, low power consumption, low lock time, are highly desirable. Such digital PLL circuit should encompass a small chip area and exemplify good performance.